1. Field of the Invention
The present invention relates to a bipolar transistor and a method of manufacturing thereof. More particularly, the present invention relates to a bipolar transistor that has a polycrystalline silicon layer formed on an emitter region, and a method of manufacturing thereof.
2. Description of the Background Art
A conventional bipolar transistor and a method of manufacturing thereof will be described hereinafter with reference to FIGS. 45-48. FIG. 45 is a sectional view of a conventional bipolar transistor having a polycrystalline silicon layer formed on an emitter region.
First, the structure of a conventional bipolar transistor will be described with reference to FIG. 45. At a main surface of a p type silicon substrate 1, a collector region 2 is formed. A p type base region 3 is formed at the surface of collector region 2. An n type emitter region 4 is formed at the surface of base region 3.
On the main surface of silicon substrate 1, an insulation layer 5 including a contact hole 6 is formed on emitter region 4. Insulation layer 5 is formed of, for example, a silicon oxide film. A polycrystalline silicon layer 7 is formed so as to extend from contact hole 6 onto insulation layer 5. An interlayer insulation layer 8 such as of a silicon oxide film is formed so as to cover polycrystalline silicon layer 7.
Contact holes 9a and 9c are formed through interlayer insulation layer 8 and insulation layer 5 to reach a surface of collector region 2 and a base region 3, respectively. A contact hole 9b is formed through interlayer insulation layer 8 to reach the surface of polycrystalline silicon layer 7. A metal electrode 10 is formed within contact holes 9a, 9b, and 9c.
A method of manufacturing the conventional bipolar transistor of FIG. 45 will be described hereinafter with reference to FIGS. 46-48.
Referring to FIG. 46, an n type collector region 2 and a p type base region 3 are formed at desired regions in the main surface of a p type silicon substrate 1 by ion implantation or the like. Then, an insulation film 5 such as a silicon oxide film is deposited on the main surface of silicon substrate 1 by CVD (Chemical Vapor Deposition). A resist pattern 11j having an opening where emitter region 4 is to be formed is provided on insulation layer 5 by photolithography. Using this resist pattern 11j as a mask, insulation layer 5 is etched to form contact hole 6. Then, resist pattern 11j is removed.
Referring to FIG. 47, polycrystalline silicon layer 7 is formed within contact hole 6 and over insulation layer 5 by CVD. Then, n type impurities are introduced into polycrystalline silicon layer 7. Polycrystalline silicon layer 7 is patterned to a predetermined configuration. Polycrystalline silicon layer 7 is subjected to a thermal treatment, whereby the n type impurities within polycrystalline silicon layer 7 are diffused into base region 3. As a result, an emitter region 4 of shallow diffusion is formed.
Referring to FIG. 48, interlayer insulation layer 8 is formed so as to cover polycrystalline silicon layer 7 and insulation layer 5. On interlayer insulation layer 8, a resist pattern 11k is formed having a predetermined configuration including an opening for the formation of contact holes 9a, 9b and 9c. Using resist pattern 11k as a mask, interlayer insulation layer 8 and insulation layer 5 are etched. As a result, contact holes 9a, 9b and 9c are formed. Then, resist pattern 11k is removed. Metal electrode 10 is formed in each of contact holes 9a, 9b and 9c by sputtering. Thus, the conventional bipolar transistor shown in FIG. 45 is formed.
The above-described conventional bipolar transistor has problems set forth in the following.
Referring to FIG. 49, the above-described conventional bipolar transistor has a polycrystalline silicon layer 7 between emitter region 4 and metal electrode 10. Since polycrystalline silicon has a resistance higher than that of metal, the presence of polycrystalline silicon layer 7 between emitter region 4 and metal electrode 10 provides a relatively high resistance R between emitter region 4 and metal electrode 10. As a result, the emitter resistance is increased to degrade the operating speed of the bipolar transistor.
An approach can be considered of forming direct contact between metal electrode 10 and emitter region 4 without forming polycrystalline silicon layer 7 as shown in FIG. 50 in order to reduce the emitter resistance. FIG. 50 is a sectional view of a conventional bipolar transistor where direct contact is provided between emitter region 4 and metal electrode 10 with no formation of polycrystalline silicon layer on emitter region 4. It is appreciated from FIG. 50 that the emitter resistance can be reduced by the direct contact of metal electrode 10 and emitter region 4.
However, the bipolar transistor of FIG. 50 has a problem which will be described hereinafter with reference to FIGS. 51 and 52.
Referring to FIG. 51, the method of manufacturing the bipolar transistor of FIG. 50 includes the steps of forming emitter region 4 by photolithography and ion implantation, forming interlayer insulation layer 8, and forming a contact hole 9 for providing metal electrode 10 in interlayer insulation layer 8. Contact hole 9 is generally provided by photolithography.
More specifically, as shown in FIG. 51, a resist pattern 11m is used as a mask in the formation of emitter region 4, and resist pattern 11l is used as a mask in the formation of contact hole 9. This means that an overlapping margin W4 must be provided for resist patterns 11m and 11l.
Therefore, the emitter width W3 cannot be made smaller than the dimension of 2.times.W4. As a result, the dimension of emitter width W3 is relatively increased. It is known that a smaller emitter width W3 allows a higher speed operation in a bipolar transistor. Therefore, such an increase in emitter width W3 induces the problem of degradation in speed of the bipolar transistor.
An approach can be considered of forming emitter region 4 after formation of contact hole 9 as shown in FIG. 52 in order to solve the above-described problem with emitter width W3. In this case, the emitter width can be reduced to W5 since it is not necessary to provide the above-described overlapping margin W4. Therefore, the problem of degradation in the speed of the bipolar transistor caused by increase of the emitter width can be avoided. However, since emitter region 4 can be formed only by ion implantation, there is the problem that the depth D of emitter region 4 is increased. It is known that a smaller depth D of emitter region 4 allows a higher speed operation of the bipolar transistor. Therefore, the problem of degradation in the speed of the bipolar transistor is not solved.
The above-described problem caused by increase in the emitter width W3 and the depth D of emitter region 4 is not encountered in a bipolar transistor that has a polycrystalline silicon layer formed on emitter region 4. This is because emitter region 4 is formed by diffusing the impurities in polycrystalline silicon layer 7 into base region 3. In view of the foregoing, it is preferable to use a bipolar transistor that has a polycrystalline silicon layer formed on an emitter region from the stand point of high speed operation of a bipolar transistor. However, such a bipolar transistor had the problem that the emitter resistance is increased, as described before.